Field programmable gate arrays (FPGAs) may be designed to support a variety of high-speed serial standards with speeds ranging from several hundreds of megahertz (MHz) to several decades of gigahertz (GHz). Such requirements mandate the use of a frequency synthesizer phase lock loop (PLL) whose output frequency can range over multiple decades of gigahertz. Current transceivers resolve this issue by using multiple parallel voltage controlled oscillators (VCOs), each of which produces the required output frequency over a different fraction of the desired frequency spectrum. However, this solution requires a large area of silicon due to the need for multiple inductor-capacitor voltage controlled oscillators (LC VCOs), which have large inductor coils. One or more embodiments described below address these issues.